The invention relates to a pipelined digital processor which is described more particularly as a processor arranged for conditional operations.
Stored program control digital computers typically include a memory, input-output circuitry, a controller and arithmetic section. The memory provides a source for a computer program and data to be operated on by the arithmetic section. The arithmetic section includes circuits which provide means for manipulating data in a predetermined manner. The controller provides control signals for regulating timing and transfers of data to be operated upon. The input-output circuitry provides means for transferring information between the computer and external devices. Some operations of the computer may be conditioned upon flags, or conditions, existing as a result of prior operations or other events.
To increase computational speed, some digital computers are arranged for pipelined operation. In a pipelined operation the arithmetic unit, or section, includes a collection of specialized circuits capable of working simultaneously but altogether forming a general purpose organization. These specialized circuits operate independently, each performing a specific task in a general purpose procedure. The pipelined operation divides a process into several subprocesses which are executed by the individual specialized circuits. Successive ones of the subprocesses are carried out in an overlapped mode analogous to an industrial assembly line. New operands are applied at the input to the arithmetic section during each cycle. Different subsections of the arithmetic section perform their tasks in sequential order during subsequent cycles. A resultant is produced each cycle. Each specialized circuit performs its own task at the cyclic rate.
Control of a pipelined computer, or processor, presents particularly perplexing problems when operations are to be executed conditionally because instructions become stacked up in the pipeline during steady-state operation.
Heretofore a pipelined digital processor has been designed to transfer data words and instructions from memory to the arithmetic section and a control section in respective pipelined streams. These streams of data words and instruction words fill pipelines of circuits within the processor. As long as the processor operates normally, the pipelines of information are processed step by step through sections of the processor in a cyclical operation.
A problem arises, however, when an operation must be executed conditionally. Typically this operation is realized by a conditional transfer that causes execution of one of two alternative sequences of one or more instructions. Since one of these sequences of instructions is in the processor pipeline when the condition is tested, it may be necessary to abort execution of that sequence and start to fill the pipeline for execution of the alternative sequence. Processing time is lost whenever this alternate sequence is invoked.